1. Field of the Invention
The present invention relates to a driver circuit of a semiconductor display device (hereinafter referred to as display device), and to a display device provided with the driver circuit. More particularly, the present invention relates to a driver circuit of an active matrix display device having a thin film transistor formed on an insulator and an active matrix display device provided with the driver circuit. Of those, in particular, the present invention relates to a driver circuit of an active matrix liquid crystal display device using a digital image signal as an image source and an active matrix liquid crystal display device provided with the driver circuit.
2. Description of the Related Art
Recently, the spreading of a display device formed with a semiconductor thin film on an insulator, particularly on a glass substrate, and in particular to an active matrix display device provided with the thin film transistor (hereinafter referred to as TFT) is significant. The active matrix display device using a TFT has several hundred thousands to several millions of TFTs arranged in a matrix, and the display of images are performed by controlling an electric field of each pixel.
Further, recently, techniques relating to polysilicon TFTs which simultaneously form a driver circuit using TFTs in the periphery of a pixel portion, in addition to pixel TFTs structuring the pixel is developing. This technique greatly contributes to miniaturization of a device and low power consumption, and in addition to that, the liquid crystal display device is becoming an indispensable device to a display portion or the like of mobile equipment which has significantly increased field of use recently.
A schematic diagram of a normal digital method liquid crystal display device is shown in FIG. 13. A pixel portion 1308 is arranged in the center. On the upper side of the pixel portion is a source signal line driver circuit 1301 for controlling the source signal line. The source signal line driver circuit 1301 is comprised of a first latch circuit 1304, a second latch circuit 1305, a D/A converter circuit 1306, an analog switch 1307 and the like. On the right and left side of the pixel portion is arranged a gate signal line driver circuit 1302 for controlling the gate signal line. Note that, in FIG. 13 the gate signal line driver circuit 1302 is arranged on both the right and left side of the pixel portion, but may be arranged on only one side. However, it is preferable from the point of view of the driver efficiency and driver reliability that they are arranged on both sides of the pixel portion.
The source signal line driver circuit 1301 has a structure as shown in FIG. 14. The driver circuit shown as an example in FIG. 14 is a source signal line driver circuit corresponding to a display of a horizontal resolution of 1024 pixels and a 3 bit digital tone, and comprises a shift register circuit (SR) 1401, a first latch circuit (LAT1) 1402, a second latch circuit (LAT2) 1403, a D/A converter circuit (D/A) 1404 or the like. Note that, although not shown in FIG. 14, a buffer circuit, a level shift circuit or the like may be arranged if necessary.
The operations are described briefly with reference to FIGS. 13 and 14. First, a shift register circuit 1303 (shown as SR in FIG. 14) is input with a clock signal (S-CLK, S-CLKb) and a start pulse (S-SP), and is sequentially output with a sampling pulse. Subsequently, the sampling pulse is input to the first latch circuit 1304 (shown as LAT1 in FIG. 14), and a digital image signal (digital data) also input to the first latch circuit 1304 are respectively maintained. This period is referred to as a dot data sampling period. Here, D1 is the most significant bit (MSB: most significant bit) and D3 is the least significant bit (LSB: least significant bit). In the first latch circuit 1304 when holding of digital image signals for one horizontal period is completed, the digital image signals held in the first latch circuit 1304 are all transferred at once to the second latch circuit 1305 (shown as LAT2 in FIG. 14) according to the input of a latch signal (latch pulse) in a retrace period. The period the digital image signal is transferred from the first latch circuit to the second latch circuit is referred to as a line data latch period.
Thereafter, the shift register circuit 1303 operates again and storing of the digital image signal for the next horizontal period is started. At the same time, the digital image signal stored in the second latch circuit 1305 is converted to an analog image signal by the D/A converter circuit 1306 (shown as DAC in FIG. 14). This digital image signal which is made analog is written in the pixel through the source signal line. By repeating this operation display of the pixel is performed.
In a typical active matrix liquid crystal display device, in order to display a dynamic image smoothly, an updating of the image display is performed approximately 60 times in one second. That is, a digital image signal is supplied to every one frame, and needs to be written in to the pixel every time. Even if the image is a still image, the same signal has to be supplied for every one frame, thus it is necessary for the driver circuit to repeat the processing of the same digital image signal continuously.
There is a method of temporarily writing in the digital image signal of a still image to the external storage circuit and thereafter supplying the digital image signal from the external storage circuit to the liquid crystal display device for every one frame, but in either case the external storage circuit and the driver circuit need to continue to operate.
Particularly, in mobile equipment, low power consumption is greatly desired. Further, although the mobile equipment is mostly used in a still image mode, as described above, since the driver circuit continues to operate when displaying a still image, low power consumption is obstructed.